This invention relates to a semiconductor device and, more particularly, a high withstand-voltage planar transistor device.
In this field, a so-called guard ring type element structure is known as an element structure for implementing a high withstand voltage on a bipolar planar semiconductor device, such as a planar diode and planar transistor (see Japanese Patent Publication (Kokoku) No. 40-12739).
A known guard ring type planar transistor includes a guard ring region. Upon the application of a bias potential to the base region a space charge area formed around the base region reaches the guard ring region. In consequence, it is possible to increase the withstand voltage on a junction in the neighborhood of the surface of the base region and thus to enhance the withstand voltage of the transistor in comparison with a planar transistor having no guard ring region.
However, the semiconductor device of this type is susceptible to a prevailing atmospheric humidity. Under a high-temperature and high-humidity atmosphere the surface portion of the guard ring region is readily inverted from a P type to an N type due to the prevailing atmospheric humidity, resulting in a loss of the effect of such a guard ring structure and a consequent liability to a lowered withstand voltage.
In order to eliminate such drawbacks, a planar transistor has been proposed in which three guard ring regions are provided, the middle guard ring region of which ohmic-contacts with the corresponding electrode formed on an insulating film. This arrangement permits an improvement in the degradation of the withstand voltage resulting from the atmospheric humidity, but a spark is liable to occur between electrodes upon the measurement of the withstand voltage, thus involving a greater danger of an element breakage.